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ds3911 temperature-controlled, nonvolatile, i 2 c quad dac ????????????????????????????????????????????????????????????????? maxim integrated products 1 general description the ds3911 is a quad, 10-bit delta-sigma output, nonvol - atile (nv) controller that features an on-chip temperature sensor and associated analog-to-digital converter (adc). the integrated temperature sensor indexes the up to 2 n c resolution nv lookup tables (luts), encompassing a -40 n c to +100 n c temperature range. the lut directly drives the delta-sigma digital-to-analog converter (dac) outputs. this flexible lut-based architecture allows the device to provide a temperature-compensated dac out - put with arbitrary slope. programming is accomplished by an i 2 c-compatible interface that operates at speeds of up to 400khz. applications active optical cables optical transceivers linear and nonlinear compensation instrumentation and industrial controls features s four 10-bit delta-sigma outputs s on-chip temperature sensor and adc s four temperature-indexed luts, up to 2 n c resolution s i 2 c-compatible serial interface s address pins allow up to four ds3911s to share the same i 2 c bus s 2.8v to 5.5v digital supply s -40 n c to +100 n c operating temperature range s 3mm x 5mm, 14-pin tdfn package typical operating circuit 19-5933; rev 0; 6/11 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maxim-ic.com/ds3911.related . ds3911 i 2 c slave temp sensor sda v cc gnd 3.3v r pu scl i 2 c master a1 a0 v cc 3.3v 0.1f v ref gnd v ref 3.3v 0.1f r1 100 r2 2.5v 10-bit dac eeprom lut dac0 modset laser driver apcset c1 c2 10-bit dac eeprom lut dac1 modset laser driver apcset 10-bit dac eeprom lut dac2 modset laser driver apcset 10-bit dac eeprom lut dac3 modset laser driver apcset for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
????????????????????????????????????????????????????????????????? maxim integrated products 2 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac voltage range on sda, scl, and v cc relative to gnd ................................................ -0.3v to +6.0v voltage range on dac0, dac1, dac2, dac3, v ref , a0, a1 relative to gnd .............. -0.3v to (v cc + 0.3v) continuous power dissipation (t a = +70 n c) tdfn (derate 21.7mw/ n c above +70 n c) ............... 1739.1mw operating temperature range ........................ -40 n c to +100 n c programming temperature range .................... -40 n c to +85 n c storage temperature range ............................ -55 n c to +125 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions (t a = -40 n c to +100 n c, unless otherwise noted.) dc electrical characteristics (v cc = +2.8v to +5.5v, t a = -40 n c to +100 n c, unless otherwise noted.) dac electrical characteristics (v cc = +2.8v to +5.5v, t a = -40 n c to +100 n c, unless otherwise noted.) parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.8 5.5 v input logic 1 (scl, sda, a0, a1) v ih 0.7 x v cc v cc + 0.3 v input logic 0 (scl, sda, a0, a1) v il -0.3 +0.3 x v cc v parameter symbol conditions min typ max units input leakage (sda, scl, a0, a1) i l -1 +1 f a v cc supply current i cc (note 2) 0.9 2.0 ma low-level output voltage (sda) v ol 3ma sink current 0 0.4 v i/o capacitance c i/o 5 10 pf power-on recall voltage v por (note 3) 1.6 2.7 v power-up recall delay t d (note 4) 5 ms parameter symbol conditions min typ max units delta-sigma clock frequency f ds 2.1 mhz reference voltage input (v ref ) v ref minimum 0.1 f f to gnd 2.4 v cc v output range 0 v ref v output resolution see the delta-sigma dac output and control section for details 10 bits output impedance r ds 35 100 i
????????????????????????????????????????????????????????????????? maxim integrated products 3 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac temperature sensor characteristics (v cc = +2.8v to +5.5v, t a = -40 n c to +100 n c, unless otherwise noted.) analog voltage monitoring characteristics (v cc = +2.8v to +5.5v, t a = -40 n c to +100 n c, unless otherwise noted.) i 2 c ac electrical characteristics (v cc = +2.8v to +5.5v, t a = -40 n c to +100 n c, timing referenced to v il(max) and v ih(min) , unless otherwise noted.) (see figure 1 .) parameter symbol conditions min typ max units temperature error t a = -40 n c to +100 n c q 5 n c update rate (temperature and supply conversion time) t frame 16 ms parameter symbol conditions min typ max units supply resolution lsb full-scale voltage of 6.5536v 800 f v input/supply accuracy acc at factory setting 0.25 1 %fs input supply offset v os (note 5) 0 5 lsb update rate (temperature and supply conversion time) t frame 16 ms parameter symbol conditions min typ max units scl clock frequency f scl (note 6) 0 400 khz bus free time between stop and start conditions t buf 1.3 f s hold time (repeated) start condition t hd:sta 0.6 f s low period of scl t low 1.3 f s high period of scl t high 0.6 f s data hold time t hd:dat 0 0.9 f s data setup time t su:dat 100 ns start set-up time t su:sta 0.6 f s sda and scl rise time t r (note 7) 20 + 0.1c b 300 ns sda and scl fall time t f (note 7) 20 + 0.1c b 300 ns stop set-up time t su:sto 0.6 f s sda and scl capacitive loading c b (note 7) 400 pf eeprom write time t w (note 8) 10 20 ms a0, a1 setup time t su:a before start 0.6 f s a0, a1 hold time t hd:a after stop 0.6 f s input capacitance on a0, a1, sda, or scl c i 5 10 pf startup time t st 2 ms
????????????????????????????????????????????????????????????????? maxim integrated products 4 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac nonvolatile memory characteristics (v cc = +2.8v to +5.5v, unless otherwise noted.) note 1: all voltages are referenced to ground. currents entering the device are specified as positive, and currents exiting the device are specified as negative. note 2: i cc is specified with scl = sda = v cc , and en bit = 1. typical values are at v cc = 3.3v and t a = +25 n c. note 3: this is the minimum v cc voltage that causes nv memory to be recalled. note 4: this is the time from v cc > v por until initial memory recall is complete. note 5: guaranteed by design. note 6: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c stan - dard-mode timing. note 7: c b = total capacitance of one bus line in pf. note 8: eeprom write time begins after a stop condition occurs. note 9: guaranteed by characterization. figure 1. i 2 c timing diagram parameter symbol conditions min typ max units eeprom write cycles (note 9) t a = +85 n c 10,000 writes t a = +25 n c 50,000 scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low
????????????????????????????????????????????????????????????????? maxim integrated products 5 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac typical operating characteristics (t a = +25c, unless otherwise noted.) v ref current vs. dac1 code sweep (current sink filter) ds3911 toc08 dac1 value v ref (ma) 1000 800 600 400 200 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0 v ref current vs. dac0 code sweep (voltage output filter) ds3911 toc07 dac0 value v ref (ma) 1000 800 600 400 200 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0 dac1 deviation from average current vs. dac3 code sweep (both current sink filters) ds3911 toc06 dac3 value 1.25v source current (na) 1000 800 600 400 200 -400 -200 0 200 400 600 -600 0 dac1 value = 0000h dac0 value = 8000h dac1 value = ffc0h filtered dac0 voltage variation from ideal vs. dac2 code sweep (both voltage output filters) ds3911 toc05 dac2 value voltage variation from ideal (v) 1000 800 600 400 200 -1000 -800 -600 -400 -200 0 200 400 600 800 1000 1200 -1200 0 dac0 value = 0000h dac0 value = ffc0h dac0 value = 8000h inl vs. output code (current sink filter) ds3911 toc04 dac value lsb 1000 800 600 400 200 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 -14 0 inl vs. output code (voltage output filter) ds3911 toc03 dac value lsb 1000 800 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 600 400 200 supply current vs. supply voltage ds3911 toc02 v dd (v) i dd (ma) 5.4 5.1 4.5 4.8 3.3 3.6 3.9 4.2 3.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 2.7 t a = +25c supply current vs. temperature ds3911 toc01 temperature (c) i dd (ma) 100 80 -20 0 20 40 60 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 0.5 -40 120 v dd = 3.3v
????????????????????????????????????????????????????????????????? maxim integrated products 6 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac multiple device connection diagram ds3911 i 2 c slave temp sensor sda v ref scl i 2 c master i 2 c address a1 a0 3.3v 3.3v 0.1f 0.1f 63 v cc v cc 10-bit dac eeprom modset laser driver biasset 10-bit dac 10-bit dac modset laser driver biasset 10-bit dac lut lut lut lut ds3911 i 2 c slave temp sensor sda v ref 3.3v r pu scl i 2 c address a1 a0 3.3v 10-bit dac eeprom modset laser driver biasset 10-bit dac 10-bit dac modset laser driver biasset 10-bit dac lut lut lut lut 2.5v
????????????????????????????????????????????????????????????????? maxim integrated products 7 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac pin configuration pin description pin name type function 1 dac0 output delta-sigma dac output 2 dac1 output delta-sigma dac output 3 v ref input dac reference voltage input 4 gnd supply ground 5 dac2 output delta-sigma dac output 6 dac3 output delta-sigma dac output 7, 8 n.c. no internal connection 9 gnd supply ground 10 a1 input i 2 c slave address input 11 a0 input i 2 c slave address input 12 sda i/o 2-wire serial data 13 scl input 2-wire clock 14 v cc supply positive supply ep exposed pad. connect to ground. top view tdfn (3mm x 5mm) 1 dac0 2 dac1 3 v ref 4 gnd 5 dac2 6 dac3 7 n.c. 14 v cc ep 13 scl 12 sda 11 a0 10 a1 9 gnd 8 n.c. + ds3911
????????????????????????????????????????????????????????????????? maxim integrated products 8 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac detailed description the ds3911 operates in one of two modes: lookup table (lut) mode or digital-to-analog converter (dac) mode. in lut mode, the dacs output is controlled as a func - tion of the temperature measured by the devices internal temperature sensor and the pulse-density modulation profile stored in the associated dacs lut. in dac mode, the dacs output is controlled by the specific dacs dac value register ( dac0 value , dac1 value , dac2 value , and dac3 value ) using the i 2 c interface. detailed descriptions of these modes as well as additional device features are discussed in subsequent sections. delta-sigma dac output and control four delta-sigma dac outputs are provided, dac0 to dac3. with the addition of an external rc filter, these outputs provide four 10-bit resolution-analog outputs with the full-scale range set by the input v ref pin. each output is either manually controlled or controlled using a temperature-indexed lut. a delta-sigma converter pro - duces a digital output using pulse-density modulation. it provides much lower output ripple than a standard digital pwm output, given the same clock rate and filter components. figure 2 shows two recommended filters. these external rc filter components are chosen to greatly reduce the output ripple while maintaining the desired response time. using resistors smaller than the recommended val - ues can degrade the output accuracy. the devices delta-sigma outputs are 10 bits. for illus - trative purposes, a 3-bit example is provided. figure 3 shows each possible output of this 3-bit delta-sigma dac. the reference input voltage, v ref , is the supply voltage for the output buffer of all dacs. the power supply con - nected to v ref must be able to support the edge-rate requirements of the delta-sigma outputs. in a typical application, a 0.1 f f capacitor should be connected between the v ref and gnd pins. figure 2. recommended rc filter for dac outputs figure 3. 3-bit (8-position) delta-sigma example ds3911 dac 1k 1k 0.1f 0.1f voltage output ds3911 dac 1k 1k 0.1f 0.1f current sink 2k 1 2 3 4 5 6 7 0 dac ouput dac value register setting (3-bit example)
????????????????????????????????????????????????????????????????? maxim integrated products 9 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac dac power-on values each 10-bit dac is controlled directly by the value in its corresponding dac value register. each dac also has a dac por register that contains the power-on-reset (por) value for the associated dac, along with two con - trol bits: enable (en) and polarity (pol). see the lower memory register descriptions section for complete lower memory descriptions. the dac por ( dac0 por , dac1 por , dac2 por , and dac3 por ) registers are shadowed eeprom with func - tionality controlled by the shadow eeprom bit ( see ). if the see bit is high, the dac por registers function as sram only. if the see bit is low, the registers are shad - owed eeprom and eeprom write timing, t w , must be observed. on power-up, the initial dac settings are always trans - ferred from the dac por registers to the corresponding dac value registers. manual control mode on power-up, the device starts performing temperature conversions and the dac value register whose corre - sponding en bit is set is updated by the lut controller as described in the lookup table mode section. clearing the en bit enables i 2 c writes to the corresponding dac value and disables lut controller updates. this allows the indi - vidual dacs whose en bit is cleared to be controlled by writing the corresponding dac value register directly. lookup table mode the device has four nonvolatile memory tables, one for each of the four dacs. each memory table is associated with an individual dac as follows: table 04h (dac0), table 05h (dac1), table 06h (dac2), table 07h (dac3), and selected by setting the table select bits, ts[3:0], in the ctrl regis - ter. each dac memory table consists of a dac lut table (addresses 80hCafh) ( dac0 lut , dac1 lut , dac2 lut , and dac3 lut ) and a dac offset table (addresses f8hCffh) ( dac0 offset , dac1 offset , dac2 offset , and dac3 offset ). because these four memory tables all share the same address and register mapping, the ts[3:0] bits must be used to select among them. each lut address represents as little as a 2 n change in temperature. table 1 shows the full temperature-to- register mapping. the first dac offset address corresponds to 32 n of temperature. after this, every 16 n of temperature con - verts into one dac offset address slot. table 2 shows the full temperature-to-register mapping. the tindex register points to a lut address slot. the tindex register can operate in two modes, as defined by the aen bit. when the aen bit is cleared, i 2 c writes to the tindex register are enabled, and updates from the lut controller are blocked. the register can be used to force dac updates to be based on the user-selected index. the tindex register directly addresses the lut table 1. lut temperature mapping table 2. offset temperature mapping row (hex) byte0 byte1 byte2 byte3 byte4 byte5 byte6 byte7 4 n clut 80h < -36 n -36 n -32 n -28 n -24 n -20 n -16 n -12 n 88h -8 n -4 n 0 n +4 n +8 n +12 n +16 n +20 n 90h +24 n +28 n +32 n +36 n +40 n +44 n +48 n +52 n 2 n clut 98h +56 n +58 n +60 n +62 n +64 n +66 n +68 n +70 n a0h +72 n +74 n +76 n +78 n +80 n +82 n +84 n +86 n a8h +88 n +90 n +92 n +94 n +96 n +98 n +100 n r +102 n row (hex) byte0 byte1 byte2 byte3 byte4 byte5 byte6 byte7 f8h < -8 n -8 n +8 n +24 n +40 n +56 n +72 n r +88 n
???????????????????????????????????????????????????????????????? maxim integrated products 10 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac memory locations by dropping tindex [7] and forcing it high. when aen = 0, any address between 80h and ffh can be addressed. to get known results in the dac value register, tindex should be kept between 80h and afh. the device monitors the internal temperature by repeat - edly polling the temperature sensors result at a rate of t frame . each cycle, for the dac whose corresponding en bit is set, the device reads the internal temperature once, and, based on that temperature, calculates the tindex register. the tindex value corresponds directly to the lut memory address for the given temperature ranges. the dac offset address is calculated based on the tindex value so only one pointer is necessary. these two locations provide the values that eventually become the 10-bit dac input, dac value . this data that gets loaded into the dac value register is a math function of the temperature-indexed lut value and the temperature-indexed offset value, as follows: dac[9:0] = lut setting + 4 x offset setting where the dac[9:0] dac control value is left-justified in the 16-bit dac value register. dac value [15:0] = dac[9:0] x 64 example calculation for dac1: assumptions: 1) temperature is 43 n c. 2) dac1 offset index associated with 43 n c is memory table location fch and contains data = 2ah. 3) dac1 lut index associated with 43 n c is memory table location 94h and contains data = 7bh. dac1 = 7bh + 4 x 2ah = 123h = 291 dac1 value = 291 x 64 note: loss of information occurs if the result of the dac value math function described above is greater than 10 bits. it is important to set the dac value and dac offset values to ensure this overflow does not occur. the eight dac offset registers can be independ - ently set to achieve any desired temperature coefficient (tempco) on its associated dac. figure 4 demonstrates figure 4. dac offset lut examples dac offset luts eight registers per dac 0 255 511 delta-sigma dacs 767 1023 each offset register can be independently set between 0 and 1020. 1020 = 4 x ffh. this example illustrates positive and negatve tempco. dac lut bits 7:0 f8h dac lut bits 7:0 f9h dac lut bits 7:0 fah dac lut bits 7:0 fbh dac lut bits 7:0 fch dac lut bits 7:0 fdh dac lut bits 7:0 feh dac lut bits 7:0 ffh 0 255 511 -40c -8c +8c +24c +40c +56c +70c +88c +104c delta-sigma dacs 767 1023 each offset register can be independently set between 0 and 1020. 1020 = 4 x ffh. this example illustrates positive tempco. dac lut bits 7:0 f8h dac lut bits 7:0 f9h dac lut bits 7:0 fah dac lut bits 7:0 fbh dac lut bits 7:0 fch dac lut bits 7:0 fdh dac lut bits 7:0 feh dac lut bits 7:0 ffh dac offset luts eight registers per dac -40c -8c +8c +24c +40c +56c +70c +88c +104c offset memory locations for the given temperature
???????????????????????????????????????????????????????????????? maxim integrated products 11 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac how a positive and negative tempco can be achieved by adjusting dac offset values. the dacs are updated after each temperature conversion. the lut features 1 n c hysteresis to prevent chatter- hysteresis to prevent chatter - ing if the measured temperature falls on the boundary between two windows ( figure 5 ). this 1 n c hysteresis is implemented in the tindex register value calculation by adding 1 n c to temperature changes of negative slope. temperature conversion and supply voltage monitoring temperature conversion the device features an internal 12-bit temperature sensor that can drive the lut and provide a measurement of the ambient temperature over i 2 c by reading the value stored in memory addresses 04hC05h. the sensor is functional over the entire operating temperature range, and the results are stored in signed twos-complement format with a 1/16 n c resolution. see the lower memory, register 04hC05h: temp value section for the temperature sensors bit weights. the donetemp bit located in the ctrl register indicates whether a temperature conversion has been completed since the bit was last cleared. supply voltage monitoring the device also features an internal 13-bit supply voltage (v cc ) monitor. a left-justified value of the supply voltage measurement can be read over i 2 c at memory address - es 06hC07h. to calculate the supply voltage, simply convert the hexadecimal result into decimal and then multiply it by the lsb as shown in the analog voltage monitoring characteristics electrical specifications table. the donevcc bit located in the ctrl register indicates whether a v cc conversion has been completed since the bit was last cleared. slave address byte and address pins the slave address byte consists of a 7-bit slave address plus a r/ w bit, as shown in figure 6 . the devices slave address is determined by the state of the a0 and a1 address pins. these pins allow up to four devices to reside on the same i 2 c bus. address pins connected to gnd result in a 0 in the corresponding bit position in the slave address. conversely, address pins connected to v cc result in a 1 in the corresponding bit positions. for example, the devices slave address byte is b0h when a0 and a1 are grounded. see the i 2 c serial interface section for more information. i 2 c serial interface i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. see the timing diagram ( figure 1 ) and the i 2 c ac electrical characteristics table for additional information. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the masters request. bus idle or not busy: time between stop and start conditions when both sda and scl are inac - tive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. figure 5. lut hysteresis figure 6. ds3911 slave address byte memory location 9d decreasing temperature increasing temperature 1c hysteresis window temperature (c) 56 58 60 62 64 66 9c 9b 9a 99 98 1 0 1 1 r /w a0 a1 0 msb lsb slave address* *the slave address is determined by address pins a0 and a1. read/write bit
???????????????????????????????????????????????????????????????? maxim integrated products 12 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. repeated start condition: the master can use a repeated start condition at the end of one data trans - fer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a normal start condition. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements. data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses including when it is reading bits from the slave. acknowledge (ack and nack): an acknowledge (ack) or not-acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiv - ing data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device performs a nack by transmitting a one (done by releasing sda) during the 9th bit. timing for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data (see figure 7 ). a nack is used to terminate a read sequence, or used as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa - tion transferred from the master to the slave (most sig - nificant bit first) plus a 1-bit acknowledgment from the slave to the master. the 8 bits transmitted by the mas - ter are done according to the bit write definition and the acknowledgment is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the devices slave address is determined by the state of the a0 and a1 address pins as shown in figure 6 . address pins connected to gnd result in a 0 in the corre - sponding bit position in the slave address. conversely, address pins connected to v cc result in a 1 in the corresponding bit positions. when the r/ w bit is 0 (such as in b0h), the master is indicating it will write data to the slave. if r/ w is set to 1 (b1h in this case), the master is indicating it wants to read from the slave. if an incorrect (nonmatching) slave address is written, the device assumes the master is communicating with another i 2 c device and ignores the communication until the next start condition is sent. memory address: during an i 2 c write operation to the device, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c communication see figure 7 for i 2 c communication examples. writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. the mas - ter must read the slaves acknowledgement during all byte write operations. when writing to the device, the dacs output adjusts to the new setting once it has acknowledged the new data that is being written, and writes to the eeprom are written following the stop condition at the end of the write command. writing multiple bytes to a slave: i 2 c write opera - tions of multiple bytes can also be performed. during a single write sequence, up to 8 bytes in one page
???????????????????????????????????????????????????????????????? maxim integrated products 13 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac can be written at one time. if more than 8 bytes are transmitted in the sequence, only the last 8 transmit - ted bytes are stored. after the last physical memory location in a particular page (8-byte page write), the address counter automatically wraps back to the first location in the same page for subsequent byte write operations. acknowledge polling: any time a eeprom byte is written, the device requires the eeprom write time (t w ) after the stop condition to write the contents of the byte to eeprom. during the eeprom write time, the device does not acknowledge its slave address because it is busy. it is possible to take advantage of this phenomenon by repeatedly addressing the device, which allows communication to continue as soon as the device is ready. the alternative to acknowl - edge polling is to wait for a maximum period of t w to elapse before attempting to access the device. reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. however, since requiring the master to keep track of the memory address coun - ter is impractical, the next method should be used to perform reads from a specified memory location. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condi - tion, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. recall that the master must nack the last byte to inform the slave that no additional bytes are to be read. see figure 7 for i 2 c communication examples. reading multiple bytes from a slave: the read operation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the master reads the last byte, it must nack to indicate the end of the transfer and generates a stop condition. during a single read sequence of multiple figure 7. i 2 c communication examples start start stop slave ack slave ack stop repeated start master nack 1 0 1 1 0 0 0 0 b0h 0 0 0 0 0 0 0 0 00h data slave ack start slave ack 1 0 1 1 0 0 0 0 b0h 1 0 1 1 0 0 0 1 b1h 0 0 0 0 0 0 0 1 01h slave ack slave ack stop data into 00h stop slave ack stop data into 81h data start slave ack 1 0 1 1 0 0 0 0 b0h 1 0 0 0 0 0 0 0 80h slave ack slave ack data into 80h data slave ack data in 01h data repeated start master ack start slave ack 1 0 1 1 0 0 0 0 b0h 1 0 1 1 0 0 0 1 b1h 0 0 0 0 0 1 0 0 04h slave ack slave ack data in 04h data master nack data in 05h data example i 2 c transactions with b0h as the device address (when a0 and a1 are connected to gnd) *the slave address is determined by address pins a0 and a1. typical i 2 c write transaction single-byte write -write control register (00h) a) 2-byte write -write lut values for registers (80h?81h) c) single-byte read -read mode register (01h) b) 2-byte read -read temperature register (04h?05h) d) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 register address msb lsb b7 b6 b5 b4 b3 b2 b1 b0 data slave ack slave ack slave address* 1 0 1 1 0 a1 a0 r/w msb lsb read/ write
???????????????????????????????????????????????????????????????? maxim integrated products 14 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac bytes, after the last address counter position of ffh is accessed, the address counter automatically wraps back to the first location, 00h. read operations can continue indefinitely. i 2 c lut lockout both the i 2 c port and the lut controller have access to the luts. to prevent bus/data contention, the lut con - troller goes into a wait state instead of accessing the lut if the i 2 c port is active. register updates and memory access are briefly described below. ? after a voltage or temperature conversion completes or the tindex register is calculated, the results are loaded into a shadow sram for the associated regis - ter by a backdoor that is not seen by the i 2 c port. the value is pushed forward to the sram cell seen by the i 2 c port at a later state. it is not pushed if the i 2 c port is active. ? after tindex is calculated and loaded into the shad - ow sram, the lut controller goes into a round-robin loop where it updates the vcc value , temp value , and tindex registers, reads the dac offset and dac lut , performs the calculation, and loads the result into the dac value register. this process is where contention could occur. as such, the state machine waits until i 2 c is inactive before performing this process. if the i 2 c port were to become active for a long time period, the temperature compensation does not run. memory description the devices internal memory consists of both volatile and nonvolatile registers located in lower memory and four separate memory tables (upper memory), as shown in figure 8 . the lower memory is addressed from 00hC7fh. lower memory contains temperature reading, v cc reading, status bits, control registers, table select bits, and all four dac value and dac por registers. the upper memory consists of the following four memory tables. the table select bits, ts[3:0], determine which table is currently accessible through i 2 c at memory loca - tion 80hCffh. table 04h contains a nonvolatile temperature-indexed dac0 lut and dac0 offset register designed to hold the pulse-density modulation profile for dac0. table 05h contains a nonvolatile temperature-indexed dac1 lut and dac1 offset register designed to hold the pulse-density modulation profile for dac1. table 06h contains a nonvolatile temperature-indexed dac2 lut and dac2 offset registers designed to hold the pulse-density modulation profile for dac2. table 07h contains a nonvolatile temperature-indexed dac3 lut and dac3 offset registers designed to hold the pulse-density modulation profile for dac3. shadowed eeprom the dac por memory locations are actually shadowed eeprom and are controlled by the shadowed eeprom bit, see . by default, see is not set and these locations act as ordinary eeprom. by setting see these loca - tions function like sram cells, which allow an infinite number of write cycles without concern of wearing out the eeprom. this also eliminates the requirement for the eeprom write time, t w . because changes made with see enabled do not affect the eeprom, these changes are not retained through power cycles. the power-on value is the last value written with see disabled. this function can be used to speed up calibration and mini - mize the number of eeprom write cycles.
???????????????????????????????????????????????????????????????? maxim integrated products 15 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac figure 8. memory map ctrl 00h 02h 04h 06h 08h 10h lower memory upper memory (tables) 17h 78h afh f8h ffh 7fh 80h mode ts[3:0] = 0100b ts[3:0] = 0101b ts[3:0] = 0110b note: t ables 00hC03h and 08hC0fh do not exist . ts[3:0] = 0111b table 04h dac0 lut (48 bytes) dac0 offset (8 bytes) empty dac1 lut (48 bytes) dac1 offset (8 bytes) empty dac2 lut (48 bytes) dac2 offset (8 bytes) empty dac3 lut (48 bytes) dac3 offset (8 bytes) empty table 05h table 06h table 07h ts[3:0] are the table select bits. these bit s determine the currently selected/addressabl e upper memory table. sram tindex temp value vcc value empty empty dac values (8 bytes) dac por (8 bytes)
???????????????????????????????????????????????????????????????? maxim integrated products 16 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac register description this register map shows each byte/word (2-byte) in terms of its row and byte/word placement in the memory. the first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. each subsequent byte/ word on the row is one/two memory locations beyond the previous byte/words address. a total of 8 bytes are present on each row. see the lower memory register descriptions section for more information about each of these bytes. lower memory register map lower memory register descriptions lower memory, register 00h: ctrl lower memory addr (hex) word 0 word 1 word 2 word 3 byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 00h ctrl mode sram tindex temp value vcc value 08h 10h dac3 value dac2 value dac1 value dac0 value 78h dac3 por dac2 por dac1 por dac0 por power-on value 00h access r/w memory type volatile 00h donetemp donevcc sram sram ts3 ts2 ts1 ts0 bit 7 bit 0 bit 7 donetemp: done temp status 0 = temperature conversion in progress. 1 = temperature conversion completed since this bit was last cleared. bit 6 donevcc: done v cc status 0 = v cc conversion in progress. 1 = v cc conversion completed since this bit was last cleared. bits 5:4 sram: general-purpose sram. these bits have no affect on device operation. bits 3:0 ts[3:0]: table select. the devices memory tables are accessed by writing the desired table value in this bit field. the device only contains four addressable memory tables, 04hC07h, and therefore the values listed below are the only usable options. ts[3:0] table selected corresponding dac lut 0100b 04h 0 0101b 05h 1 0110b 06h 2 0111b 07h 3
???????????????????????????????????????????????????????????????? maxim integrated products 17 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac lower memory, register 01h: mode lower memory, register 02h: sram power-on value 00h access r/w memory type volatile 02h sram sram sram sram sram sram sram sram bit 7 bit 0 these general-purpose sram bits have no affect on device operation. power-on value 40h access r/w memory type volatile 01h see aen sram sram sram sram sram softtxd bit 7 bit 0 bit 7 see : shadowed eeprom disable 0 = enables eeprom writes to the shadowed eeprom bytes. 1 = disables eeprom writes to shadowed epprom bytes during configuration, so that the configuration of the device is not delayed by the eeprom cycle time. once the values are known, write this bit to a 0 and write the shadowed eeprom locations again for data to be written to the eeprom. bit 6 aen: automatic enable 0 = the temperature-calculated index value tindex is writable by the user and the automatic updates of calculated indexes are disabled. this allows users to interactively test their modules by controlling the indexing for the luts. the recalled values from the luts appear in the dac value registers after the next completion of a temperature conversion. 1 = the internal temperature sensor determines the value of tindex . bits 5:1 sram: general-purpose sram. these bits have no affect on device operation. bit 0 softtxd: soft transmit disable 0 = dacs operate normally. 1 = the dac outputs are forced to the bit value of the pol bit, which is located in the dacs associate dac por register. for example, when softtxd is set and pol = 1 in the dac0 por register, dac0 is forced to full- scale output, but if pol = 0, dac0 is forced to a zero output. this applies to all four dacs.
???????????????????????????????????????????????????????????????? maxim integrated products 18 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac lower memory, register 03h: tindex lower memory, register 04hC05h: temp value power-on value 0000h access r memory type volatile 04h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 05h 2 -1 2 -2 2 -3 2 -4 0 0 0 0 bit 7 bit 0 left-justified signed twos complement direct-to-temperature measurement. the lower 4 bits always return zero. the temperature reading is clamped to -128 n c and +127.9375 n c. power-on value 00h access when aen = 1: r access when aen = 0: r/w memory type volatile 03h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the tindex register is the temperature indexed address pointer. the tindex value corresponds directly to the lut memory address for the given temperature ranges. the dac offset address is calculated based on the tindex value, so only one pointer is necessary. the pointer value is calculated based on the current temperature reading (see the below equation). the calculation uses different math depending on which lut range (2 n c or 4 n c) the current temperature measurement resides in. temp 56 temp 56 temperature 40 temperature 8 tindex 128 128 4 2 < + ? = + = + a 1 n c hysteresis is implemented in the tindex value calculation by adding 1 n c to temperature changes of nega - tive slope. when the aen bit is high, the tindex register is read-only and the pointer is updated after the temperature and voltage conversions have completed. when the aen bit is cleared, i 2 c writes to the tindex register are enabled and updates from the lut controller are blocked. the register can be used to force dac updates to be based on the user-selected index. the tindex register directly addresses the lut memory locations by dropping tindex[7] and forcing it high. when aen = 0, any address between 80h and ffh can be addressed. to obtain known results in the dac value register, tindex should be kept between 80h and afh. tindex value is clamped for temperatures below -40 n c and above 102 n c.
???????????????????????????????????????????????????????????????? maxim integrated products 19 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac lower memory, register 06hC07h: vcc value lower memory, register 10hC11h: dac3 value lower memory, register 12hC13h: dac2 value lower memory, register 14hC15h: dac1 value lower memory, register 16hC17h: dac0 value power-on value 0000h access r memory type volatile 06h 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 07h 2 4 2 3 2 2 2 1 2 0 0 0 0 bit 7 bit 0 left-justified unsigned voltage measurement. to calculate the supply voltage, simply convert the hexadecimal result into decimal and then multiply it by the lsb as shown in the analog voltage monitoring characteristics electrical characteristics table. the lower 3 bits always return zero. power-on value 0000h access when en = 1: r access when en = 0: r/w memory type volatile 10h, 12h, 14h, 16h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 11h, 13h, 15h, 17h 2 1 2 0 sram sram sram sram sram sram bit 7 bit 0 these registers are the left- justified digital 10-bit value used for their associated dac output. the lower 6 bits have no effect on device operation. at por these registers are updated to the eeprom value dac por . when the en bit in dac por is set, this register is updated at the end of each temperature conversion, with the calcu - lated result of values recalled from lut and offset lut pointed to by tindex . ref dac v v dac value 1024 =
???????????????????????????????????????????????????????????????? maxim integrated products 20 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac lower memory, register 78hC79h: dac3 por lower memory, register 7ahC7bh: dac2 por lower memory, register 7chC7dh: dac1 por lower memory, register 7ehC7fh: dac0 por power-on value recalled from eeprom access r/w memory type nonvolatile (see) 78h, 7ah, 7ch, 7eh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 79h, 7bh, 7dh, 7fh 2 1 2 0 see see see see pol en bit 7 bit 0 bits 15:6 a left-justified, digital, 10-bit initial dac value. during a por these 10 bits are used to fill the corresponding dac value register. bits 5:2 see: these bits have no effect on device operation. bit 1 pol: polarity select 0 = normal dac mode, dac value = 3ffh results in full-scale output. 1 = inverted dac mode, dac value = 3ffh results in zero output. bit 0 en: lut enable 0 = dac mode: at power-on, the corresponding dac value register is loaded with the value stored in the corresponding dac por register. updates from the temperature-referenced lut and lut offset are disabled. the user can write to the dac value register to set the value for the dac. the dac value register is r/w. 1 = lut mode: at power-on, the corresponding dac value register is loaded with the value stored in the corresponding dac por register. after the first valid temperature conversion, the dac value register is loaded with the value calculated from the lut and lut offset that correspond to the measured temperature. the dac value register is read-only.
???????????????????????????????????????????????????????????????? maxim integrated products 21 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac upper memory register descriptions table 04h, register 80hCafh: dac0 lut table 05h, register 80hCafh: dac1 lut table 06h, register 80hCafh: dac2 lut table 07h, register 80hCafh: dac3 lut factory default 00h access r/w memory type nonvolatile 80hCafh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the dac lut is a set of registers assigned to hold the pulse-density modulation profile for the associated dac. the values in this table are added to four times the corresponding value in the dac offset table to determine the set point for the associated dac. in all four dac tables, the dac lut registers are formatted the same. beginning at - 40 n c, the lut increments in 4 n c steps per address until the temperature reaches 56 n c, then it increments in 2 n c steps until it clamps at 102 n c. see the lut temperature mapping table for full register-to- temperature mapping. register 80h defines the -40 n c to -36 n c dac lut value, register 81h defines the -36 n c to -32 n c dac lut value, and so on. luttemperaturemapping row (hex) byte0 byte1 byte2 byte3 byte4 byte5 byte6 byte7 4 n clut 80h < -36 n -36 n -32 n -28 n -24 n -20 n -16 n -12 n 88h -8 n -4 n 0 n +4 n +8 n +12 n +16 n +20 n 90h +24 n +28 n +32 n +36 n +40 n +44 n +48 n +52 n 2 n clut 98h +56 n +58 n +60 n +62 n +64 n +66 n +68 n +70 n a0h +72 n +74 n +76 n +78 n +80 n +82 n +84 n +86 n a8h +88 n +90 n +92 n +94 n +96 n +98 n +100 n r +102 n
???????????????????????????????????????????????????????????????? maxim integrated products 22 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac table 04h, register f8hCffh: dac0 offset table 05h, register f8hCffh: dac1 offset table 06h, register f8hCffh: dac2 offset table 07h, register f8hCffh: dac3 offset applications information power-supply decoupling to achieve the best results when using the ds3911, decouple the power supply with a 0.01 f f or 0.1 f f capac - itor. use a high-quality ceramic surface-mount capacitor if possible. surface-mount components minimize lead inductance, which improves performance, and ceram - ic capacitors tend to have adequate high-frequency response for decoupling applications. likewise, a decou - pling capacitor should be placed from v ref to gnd. sda and scl pullup resistors sda is an i/o with an open-collector output that requires a pullup resistor to realize high-logic levels. a master using either an open-collector output with a pullup resis - tor or a push-pull output driver can be used for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the i 2 c ac electrical characteristics table are within specification. a typical value for the pullup resistors is 4.7k i . factory default 00h access r/w memory type nonvolatile f8hCffh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the dac offset is a set of registers assigned to hold the pulse-density modulation profile for the associated dac. the values in this table are multiplied by four and added to the corresponding value in the lut table to determine the set point for the associated dac. in all four dac tables, the dac offset registers are formatted the same. the offset registers increase in 16 n c steps from -8 n c to +88 n c. below -8 n c the dac offset is indexed at 0xf8. see the offset temperature mapping table for full register to temperature mapping. register f8h defines the -40 n c to -8 n c dac offset value, register f9h defines the -8 n c to +8 n c dac offset value, and so on. offsettemperaturemapping row (hex) byte0 byte1 byte2 byte3 byte4 byte5 byte6 byte7 f8h < -8 n -8 n +8 n +24 n +40 n +56 n +72 n r +88 n
???????????????????????????????????????????????????????????????? maxim integrated products 23 ds3911 temperature-controlled, nonvolatile, i 2 c quad dac ordering information package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. note: contact the factory about csbga version availability. + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. * ep = exposed pad. part temp range pin-package ds3911t+ -40 n c to +100 n c 14 tdfn-ep* ds3911t+t -40 n c to +100 n c 14 tdfn-ep* package type package code outline no. land pattern no. 14 tdfn-ep t1435n+1 21-0253 90-0246
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 24 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. ds3911 temperature-controlled, nonvolatile, i 2 c quad dac revision history revision number revision date description pages changed 0 6/11 initial release

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